1. Field of the Invention
The present invention relates to a memory system and a semiconductor memory device to be employed therein, and particularly to a memory system capable of high speed data transfer and a semiconductor memory device for the same. More particularly, the present invention relates to "a SyncLink DRAM (Dynamic Random Access Memory)."
2. Description of the Background Art
Microprocessors are heightening their performance. In addition, storage capacity of DRAMs as memory devices is also increasing. However, operation speed of a DRAM is slower than that of a microprocessor, and thus large amount of data (including instructions) required by the microprocessor cannot be transferred at high speed between the DRAM and the processor. In order to meet this requirement of high speed data transfer, various types of high speed memory systems have been proposed, in which a plurality of DRAMs are connected in parallel via a bus and data transfer is performed successively in synchronization with a clock signal. In the following, a description is made of a memory system employing a "SyncLink DRAM" as its memory device, as an example of a high speed memory system.
FIG. 10A is a schematic diagram of a structure of a currently proposed memory system. Referring to FIG. 10A, the memory system includes a memory controller 1, a plurality of semiconductor memory devices (hereinafter referred to as DRAMs) DM0 to DM3 connected in parallel, a send link 10 commonly connected to these DRAMs DM0 to DM3 for transferring commands, addresses and data from controller 1, a sync link 20 commonly connected to DRAMs DM0 to DM3 for transferring data read out from these DRAMs DM0 to DM3 to controller 1, and a control signal line 30 for successively transferring control signals for setting identifiers (slave IDs) to DRAMs DM0 to DM3.
Maximum number of DRAMs which can be supported is 63. Send link 10 and sync link 20 are connected to each of the DRAMs DM0 to DM3 such that the sum of the length of the access request path from controller 1 and the length of access response (i.e., data return) path to controller 1 would be equal for all DRAMs DM0 to DM3. More specifically, sync link 20 is connected to respective DRAMs DM0 to DM3, and includes a portion for transferring data in a direction from DRAM DM0 to DRAM DM3 as well as a portion for transferring data (response) in a direction from DRAM DM3 to controller 1.
In this memory system shown in FIG. 10A, DRAMs DM0 to DM3 are uniquely allocated with an identifier (slave ID), respectively. Controller 1 uses these slave IDs to make an access to DRAMs DM0 to DM3. As for send link 10 and sync link 20 in this memory system, all of the information is sent out in a packet form. In addition, send link 10 is of an 8-bit or 9-bit width, while sync link 20 is of a 16-bit or 18-bit width. The send link 10 sends out information in synchronization with both rising and falling edges of the clock not shown, while the sync link 20 transmits information in synchronization with one of the edges of this clock signal. Also, since information is transferred by using two busses, namely send link 10 and sync link 20, when access request to DRAMs DM0 to DM3 via send link 10 occurs, data can also be read out from another DRAM via sync link 20, and thus a high speed data transfer is made possible. The slave IDs of this memory system are set as described in the following. In the following, description will be made of the setting sequence of the slave IDs with reference to FIGS. 10A to 10D.
Referring to FIG. 10A, controller 1 in broadcast mode sends a hard reset command rstHRD onto send link 10. In accordance with this hard reset command, DRAMs DM0 to DM3 set their own slave IDs at the initial value.
DRAMs DM0 to DM3 each have a select input SIN as an identifier input enable input node as well as a select output SOUT as an identifier set complete enable output node. These select input SIN and select output SOUT are interconnected by control signal line 30 through DRAMs DM0 to DM3. The DRAM can incorporate as its own identifier the value provided onto send link 10 when its select input SIN is at "1" and select output SOUT is at "0."
DRAMs DM0 to Dm3 each maintain this select output SOUT at value "0" while the slave ID is at an initial value of 62.
Referring to FIG. 10B, controller 1 sends identifier setting command cfgHRD onto send link 10 after initialization (reset) of DRAMs DM0 to DM3. This identifier setting command cfgHRD is sent out in the form of a packet which includes a node for indicating the number of the slave ID and a value to be incorporated as the identifier. Also, controller 1 sends out a signal "1" on control signal line 30 and activates select input SIN of DRAM DM0. Since DRAM DM0 has its select input SIN at an activated state "1" and its select output SOUT at an inactivated state "0," it updates the initialized slave ID value 62 to a value 0 provided onto send link 10 in accordance with this command cfgHRD.
DRAM DM0 sets this slave ID at "0" and then sends a signal of "1" to select output SOUT. Thus, DRAM DM0 indicates that setting of its identifier is completed, and enables slave ID to be input to DRAM DM1 of the next stage.
When the slave ID of DRAM DM0 is being set, DRAMs DM1 to DM3 each have its select input SIN and select output SOUT both at "0" and thus DRAMs DM1 to DM3 do not perform an identifier setting operation according to the command sent to this send link 10.
This operation shown in FIG. 10B is performed also to DRAM DM1.
Thereafter, as shown in FIG. 10C, controller 1 again sends identifier setting command cfgHRD onto send link 10. In the packet including this command, a node number as well as an identifier number (value) are also included. DRAM DM2 has its select input SIN set at "1" and select output SOUT at "0," and thus updates the slave ID from 62 to 2 according to this initial value setting command cfgHRD, and after this update of the slave ID, DRAM DM2 sets select output SOUT at "1."
Then, as shown in FIG. 10D, after a prescribed time period has passed (in other words, after a time period required for the setting of the slave ID of DRAM DM2 has passed), controller 1 again sends out identifier setting command cfgHRD along with node number 62 and value 3 as the identifier. DRAM DM3 updates its own slave ID from 62 to 3 according to this identifier setting command cfgHRD on send link 10, and outputs a signal "1" to select output SOUT. When controller 1 detects this return of signal "1" via control signal line 30, it acknowledges that setting of the slave IDs of all DRAMs, that is, DRAMs DM0 to DM3, is complete.
More specifically, controller 1 sends out this identifier setting command in repetition, successively incrementing its value until a signal "1" is returned via control signal line 30.
By returning back the signal "1", or in other words, an identifier setting complete signal via control signal line 30, it is made possible for controller 1 to successively set the slave IDs to the DRAMs included in the memory system even when it does not know how many DRAMs are included in the memory system. In addition, by returning back the identifier setting complete signal via this control signal line 30, it is made possible for controller 1 to acknowledge the number of DRAMs included in this memory system and that setting of the identifiers is complete.
In a conventional memory system, controller 1 successively increments the slave ID from 0. The value obtained by adding 1 to this slave ID indicates the distance between controller 1 and the DRAM. Accordingly, when controller 1 determines that there is an access failure during the use of this memory system, it informs the user the slave ID of the DRAM in which this access failure has occurred, so that the user can replace the defective DRAM.
However, when controller 1 does not detect this failure, the defective DRAM is put in use and there would be an erroneous operation in the system. Moreover, even if controller 1 does detect an access failure, it means that this defective DRAM has been used up to the point of time when this access failure was detected; there is no way to know with certainty that the process performed before this detection was accurate. Thus, a problem that system performance would be degraded arises.
Specifically, in the slave ID setting sequence of the DRAM, when select input SIN and select output SOUT are set at "1" and "0," respectively, the DRAM will have its slave ID set regardless of whether its internal circuit is defective or non-defective. Accordingly, the slave ID is set also to the DRAM which is already defective before the memory system is operated, and thus the defective DRAM is put into use. Therefore, there has been a problem that erroneous operation of the memory system is caused right from the time when the system has started its operation.